The requirement to achieve the lower power is constant for portable application products from portable navigation devices to cell phones. This requirement drives the most complex System on Chip (SoC) power management control functions commonly called as power-reset-clock-management (PRCM). In the prior art these functions are hardware based with limited configurability. Such hardwired functions reduce the flexibility after manufacture of the SoC. This increases the complexity of the power management control further because the prior art attempts to predict and account for all use cases. The significant complexity of this power control function, typically require significant investments of effort on chip design verification pre-silicon, post-silicon validation and debug, and finally for silicon re-spins due to bug fixes required following manufacture.
There is a need in the art to achieve very low power and flexibility for better execution efficiency. This is expected to thereby lower investment and cost.